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本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
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sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl
\doc DDR SDRAM reference design documentation
\model Contains the vhdl SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation
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9.1 异步FIFO设计实例
9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
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this document explain de function of ddr sdram controller
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