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Chapter-2
- 3.1加法树乘法器add_tree_mult设计实例, 3.2查找表乘法器lookup_mult设计实例. 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例 -3.1 adder tree multiplier add_tree_mult design example, 3.2 lookup table multiplier lookup_mult design examples. 3.3 Design Example 3.4 Bo
Chapter-3
- 3.1加法树乘法器add_tree_mult设计实例 3.2查找表乘法器lookup_mult设计实例 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例-3.1 adder tree multiplier add_tree_mult design example 3.2 multiplier lookup_mult lookup table design example 3.3 Design Example 3.4 Boolean mu
half_clk
- 此为用Verilog编写的1/2分频器,用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
clock_speed
- fpga分频器设计。将高频时钟信号任意分频-fpga crossover design. The high frequency clock signal any divider
CLOCK
- 数字钟——分频器,将开发板上的20MHZ的输入CLK转换成时分秒进位需要要到的1HZclk-Digital clock- divider, input CLK 20MHZ development board will be converted into minutes and seconds rounding need to go to the 1HZclk
VHDL-
- VHDL语言 有限状态机交通灯的设计 分频器模块的设计-Finite state machine design language VHDL design of traffic lights divider module
div_freq
- 分频器,把一个特定的频率进行分频,从而得到自己想要的频率-Frequency divider, a specific frequency divider, you want to get the frequency
my_32fp_mult
- 这是一个计算32位浮点数的除法器,ALTERA的FPGA可直接用,用VHDL语言写的,希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
jiaotongdneg
- 交通信号灯 本程序设计中用到了8253,8255,8259三个芯片。利用8253分频产生0.1S的时钟,8255连接LED灯输出,利用8259产生中断,控制交通灯的状态。-Traffic lights used in the design of this program 8253,8255,8259 three chips. The use of 8253-Divider 0.1S clock, LED light output 8255 connected by 8259 to gener
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路,利用数控分频的原理设计乐曲硬件演奏电路,并定制LPM-ROM存储音乐数据,-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
Proj2_final
- 2 4 8级流水线乘法器 以及 除法器 包括makefile 和 tcl 比较详细-248 stage pipeline multiplier and divider includes more detailed makefile and tcl