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用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
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vhdl编的cpu，自己的课程验收实验，微指令实现，流程详细。存储，加减基本运算均有，乘法使用位移相加法得到。其中excel有微程序控制信号的编码，储存ram编写，控制器rom编写等-vhdl code of cpu, its acceptance test program, microcode implementation process in detail. Storage, addition and subtraction are the basic operations, multipl
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用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
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用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
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float-point multiplication
standart IEEE-754
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multiplication app in vhdl
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This a VHDl code for multipication of 8 bits and it is generic.-This is a VHDl code for multipication of 8 bits and it is generic.
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矩阵乘法的vhdl语言版本，可以实现简单的乘法(Matrix multiplication)
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