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modelsim库编译包会教程
- 对modelsim中的vhdl和verilog库进行编译的教程和实施命令-right modelsim of VHDL and Verilog library compiler implementation of the curriculum and order
ddr2_speedway_f07_9_2_1_1
- ddr2sdram控制器入门教程，详细的说明其实现过程-Getting Started Guide ddr2sdram controller, detailed descr iption of the process of its realization