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sdgshjd
- 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple C
JPEG_Hardware_Compressor_Encod
- JPEG Hardware Compressor Encoder,JPEG Hardware Compressor Encoder
vhdl
- 3vhdl简单程序设计；4,8-3优先编码器5,3-8译码器；6,6d锁存器；7，数码管扫描显示；8，四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
16b20b_Encoder
- VHDL实现的16B/20B编码器。由两个8B/10B编码器组成。级联实现。-VHDL implementation 16B/20B encoder. Composed by two 8B/10B encoder. Cascade realization.
bianma
- 使用QUARTUS2写的循环码编码器源代码-Writing of the use of cyclic codes QUARTUS2 encoder source code
HammingDecoder
- -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee U
Pipelined_Implementation_of_Baseline_JPEG_Encoder
- Pipelined Implementation of Baseline JPEG Encoder
rs(31-19)
- 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in M
HD6409_encode
- 基于VHDL语言的HD4069曼彻斯特编码器实现-Based on VHDL HD4069 Manchester encoder implementation
BCH
- 此代码用VHDL实现BCH(57,44,6)编码器，属于信道编码的内容，此外采用Miggitt译码器实现译码功能。-This code BCH (57,44,6) encoder using VHDL, is a channel coding content, the addition Miggitt decoder decoding function.
bcd_adder
- 用vhdl实现的bcd编码器，实现bcd编码，实验程序，已经调试成功-To bcd encoder vhdl to achieve the bcd coding, experimental procedures, debugging has been successful
oc_mkjpeg_rev61_subsampling
- JPEG encoder USING vhdl CODE TO RUN FOR CHECKING THE IMAGE COMPRESSION
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
rs(63-45)
- 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.
encoder
- VHDL Code for D-Flip Flop & Matching Unit
jpeg
- Its about JPEG encoder in VHDL language