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4bit_mul_3
- It is a 4 bit s mul writed by VHDL language which is improved.
FIFOexperience
- 华为内部关于FIFO的经验之谈，深入了解FIFO-Huawei on the FIFO' s internal experiences
dianziqin
- 这是一个有关梁祝的电子琴设计代码，可能和别人的有点相识，但是还是希望大家好好看看 -This is a Butterfly s flower design code, and those of others may be a little known, but still hope that a good look at
cvery.comdel7535899835
- 学生成绩管理 实现成绩的查询 录入多个公司的JAVA面试试题，供 ·模式识别matlab工具箱,包括SV ·文件类型：Visual FoxPro 人 ·struts2.0得例子,主要是实现s ·一个C#多线程的例子。 ·卡尔曼滤波器matlab源代码。 ·很不错的vhdl学习实例 几十 ·原版的FAT32手册,E文差的同志 ·常见的JAva面试试题，平时可 ·一个小型C语言编译器 -Student performance managem
08080212109337
- 完成开锁、超时报警、超次锁定、管理员解密、修改用户密码基本的密码锁的功能-Unlock the completion of overtime alarm, lock超次, administrators declassified, modify the user s password locks the basic functions of
sopcast
- 完成开锁、超时报警、超次锁定、管理员解密、修改用户密码基本的密码锁的功能-Unlock the completion of overtime alarm, lock超次, administrators declassified, modify the user s password locks the basic functions of
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶
gprs1
- Motorola无线通讯模块G20的资料，一些关于gprs模块程序-Motorola' s G20 wireless data communication module, a number of procedures on gprs module
UART
- A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the
Finiteimpulseresponsefirfilter
- This code is a VHDL based code for FIR filter.A finite impulse response (FIR ) filter is a type of a digital filter. The impulse response, the filter s response to a Kronecker delta input, is finite because it settles to zero in a finite number of sa
code.tar
- Code for the book "The Designer s Guide to VHDL, 3rd Edition" by Peter J. Ashenden.
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
CSC_XAPP931_pdf
- This document is Xilinx`s Color Space Conversion Applcation Note. This CSC is a RGB to YCrCb Conversion.
yima
- vhdl译码的部分源代码，取自硕士学位论文，希望对大家有用。-vhdl coding parts of the source code, taken from the master' s degree thesis, we hope be useful.
bluespec-reedsolomon_latest.tar
- Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
DSSS
- 用VHDL实现基于Xilinx的FPGA上的直接序列扩频通信，并且附带了matlab仿真程序。-VHDL implementation based on direct sequence spread spectrum communication on Xilinx' s FPGA, and comes with matlab simulation program.