搜索资源列表
Vivado_Zynq_Guide
- Vivado的简明教程及Zynq的开发流程-Vivado concise tutorials and Zynq development process
xilinx_ise_vivado_2017
- vivado最新可用license2017-vivado license ok for 2017
lab1_flash_led.xpr
- Verilog语言编写led流水灯,vivado环境编写-led water lights written by verilog
mult88
- 两个8*8矩阵相乘，每个矩阵内部元素相同，简化运算；modelsim编译仿真，ise或vivado下载，实现FPGA显示。(Two 8*8 matrix multiplication, each element of the same matrix, simplifying the operation; Modelsim compiler simulation, ISE or vivado download, to achieve FPGA display.)
lab1
- Verilog lab1 is used for learning vivado
gate_test
- 使用vivado hls 对GATE代码进行封装，主要调试stream接口(using vivado hls to archieve GATE syn, to debug the AXI4-stream interface)
ddr3
- ALINX7010 ddr3读写测试仿真实验官方教程 附说明和代码 Vivado 实现(Alinx7010 DDR3 read write test simulation experiment official course Descr iption and code attached Vivado implementation)