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EDA
- EDA实验程序:60进制,数字钟 ,表决器 包括VHDL语言和图的连线-EDA experimental procedure: 60 binary, digital clock, voting Including connection VHDL language and graphs
6c39b755f84775a3d8da072f766399e0
- 本文为数字时钟的设计介绍,具体说明如何使用QuartusⅡ软件设计一个基于EP1C6Q240C8芯片的数字钟。该数字钟具备以下功能:1.正常计时2.校正时间3.闹铃设置4.整点报时。-This paper describes the design of a digital clock, specifying how to use the software to design a QuartusⅡ EP1C6Q240C8 chips based on the digital clock. The
Chapter16
- 数字钟设计,压缩文件里是工程实例,打开运行即可- U6570 u5B57 u949F u8BBE u8BB u8BBE u8BBE u8A