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- 加减计数器 library ieee use ieee. std_logic-_1164.all entity dec3_8 is port(a,b,c,s1,s2,s3: in std_logic y: out std_logic_vector(0 to 7)) end architecture b of dec3_8 is signal abc: std_logic_vector(0 t
sy1
- 28M分频器 D触发器 jk触发器 library ieee -library ieee use ieee.std_logic_1164.all use ieee.std_logic_arith.all use ieee.std_logic_unsigned.all entity ymq is port(num:in std_logic_vector(3 downto 0) dout:out std_logic_vect
sy4
- D74LS74 JK74ls112. LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY D74LS74 is port(clk,clr,PRE,D:in std_logic QT,QTN:out std_logic) end ENTITY D74LS74 architecture bhv of D74LS74 is signal q,qn:std_logic signal x:std_logic
LIBRARY-IEEE
- 加法计数器的设计 任意进制的计数器设计-LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY sun IS PORT(ENA,CLK_IN,CLR:IN STD_LOGIC Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) END sun ARCHITECTURE A OF sun IS SIGNAL CLK:STD_LOGIC SIGNAL TEMP:INTEG
library-ieee
- 3位计数器显示,可以测量1到10Mhz的频率，还可以刷新和保存数据的呢-display 3 numbers
modulation
- 基于FPGA的QPSK调制library ieee use ieee.std_logic_1164.all -FPGA QPSK modulation