Carry Look Ahead Example with VHDL code. Good code for altera platform

altera发布的开源8b10b源代码，vhdl语言描述-altera released the source code open source 8b10b, vhdl language descr iption

SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE