用VHDL写的一个SPI接口程，调试通过，曾多次用项目中，感非常好用，与大家分享。-Use VHDL to write an SPI interface process, debugging is passed, with the project on several occasions, the flu is very useful to share with you.

spi总线结构设计和实现用vhdl汇编语言编写的 -spi for verilog hardware descr iption language

SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE