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rall_gen0
- 产生霍尔信号的使用verilog语言设计代码,能产生4种马达转速的设计(960转/分钟,1440转/分钟,2880转/分钟,4800转/分钟)供参考-Generate Hall signals use the verilog language design code to produce the design of the motor speed (960 r/min, 1440 r/min, 2880 r/min to 4800 rev/min) for reference