Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M

3vhdl简单程序设计；4,8-3优先编码器5,3-8译码器；6,6d锁存器；7，数码管扫描显示；8，四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter

并行数据向串行数据的转换，实现并到串之间的随意变换-parelell to seriel

VHDL实现的16B/20B解码器。包含两个8B/10B解码器。采用级联方式实现-VHDL implementation 16B/20B decoder. Contains two 8B/10B decoder. Be achieved by cascading