搜索资源列表
turbo_VHDL
- Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M
usb_funct
- USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
1_4
- 一对四分用器的VHDL源码,（输入：D ，输出： Y3 Y2 Y1 Y0，另有两个输入控制端S1与S0控制输出选择）-tended to a quarter of VHDL source code, (Input : D, output : Y3 Y2 Y1 Y0. otherwise control the importation of two-S1 and S0 output control options)
lc2
- this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 mode
QPSKvhdl.rar
- QPSK的VHDL调制解调 FPGA设计思路思想,QPSK modulation and demodulation of the VHDL design thinking FPGA
dianziqin
- 这是一个有关梁祝的电子琴设计代码，可能和别人的有点相识，但是还是希望大家好好看看 -This is a Butterfly s flower design code, and those of others may be a little known, but still hope that a good look at
bianma
- 使用QUARTUS2写的循环码编码器源代码-Writing of the use of cyclic codes QUARTUS2 encoder source code
i2c_latest[1].tar
- I2C VHDL source code
i2c_master_slave_core_latest[1].tar
- I2C VHDL source code
i2c_master_slave_latest[1].tar
- I2C Core VHDL RTL Source Code for Synthesis
nnARM_tb01_09_02
- arm processor verilog code
VHDl
- Its a ALU code for the mathematical computations.It also has many other codes.
5
- Code for JK flip flop and SR flip flop
Subsystem_grt_rtw
- vhdl code for sub system of relational generator
job217
- 实现（2，1，7）卷积编码以及相应的viterbi译码-(2,1,7) convolutional code and the corresponding Viterbi decoding
yima
- vhdl译码的部分源代码，取自硕士学位论文，希望对大家有用。-vhdl coding parts of the source code, taken from the master' s degree thesis, we hope be useful.
QPSK_modulator_demodulator
- Wireless_Communication_FPGA设计代码之一：QPSK调制解调的FPGA实现 将相应的源文件复制到本地硬盘上，修改属性为可写，然后在ISE环境中新建工程，然后添加相应的源文件即可。-Wireless_Communication_FPGA one of the design code: QPSK modulation and demodulation of the FPGA to achieve the corresponding source files to loc
rs(31-19)
- 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in M
fft_design
- Very simple source code written in VHDL for FFT design.