用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!

硕士论文。主要包括：1、均衡器的设计原理 2、码间串扰与均衡原理 3、自适应均衡算法，主要介绍迫零算法、LMS算法、RLS算法 4、LMS自适应均衡器的Verilog设计 5、以上算法的matlab仿真-Master thesis. The main contents are as follows: 1, the design principle of the equalizer 2, intersymbol interference (ISI) and equilibrium principl