16位运算器，用实例化模块链接，是采用Verilog hdl编程，是实现fpga的代码-16-bit arithmetic unit, with links to instantiate module is using Verilog hdl programming, is to achieve the fpga code

程序并行化实例代码，需要做并行程序的朋友可以作为参考-A parallel example code, need friends can serve as a reference for parallel programs