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shixuchengfa
- 时序乘法器,8位x8位,vhdl语言.仿真验证过了.多多交流!-sequential multiplier, eight x8 spaces vhdl language. Simulation before. Interact more!
adder
- 运用VHDL语言实现四位超前进位加法器。-VHDL language using the four CLA.
Multiplier
- 用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
counter
- 运用VHDL语言实现的，功能是实现可控计数器。-The use of VHDL language, the function is to achieve controllable counter.
control
- 四位微程序控制器的指令译码器，运用VHDL语言实现。-Four micro-program controller instruction decoder using VHDL language.
RISC32bitwithVHDL
- 一个VHDL写的32位RISC程序，比较适合作为修改指令用。-32bit RISC design with VHDL language.
uart16750_latest[1].tar
- uart 16750 core discripe with VHDL language
8.9-ASK-of-VHDL
- ASK调制VHDL程序及仿真:基于VHDL硬件描述语言，对基带信号进行ASK振幅调制-ASK modulation and VHDL simulation: based on the VHDL hardware descr iption language ASK amplitude modulation, the baseband signal
xinhao
- VHDL语言的波形发生器的设计过程和使用-The design process and use of the VHDL language waveform generator
laser-echo-measurement
- 基于FPGA激光回波测时 VHDL语言实现-FPGA-based VHDL language when laser echo measurement
my_32fp_mult
- 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need