搜索资源列表
FIFO
- 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
RX_FARM_24_DATA
- verilog代码，串口接收程序，有协议-Verilog code, the receiver program, agreement
UART
- 串口及其测试向量程序,VERILOG 代码-Serial and test vector program
Example-b3-1
- Verilog/VHDL源码的串口示例，“Altera设计基础篇”第3章的串口示例，包括源码和仿真文件等-Verilog/VHDL source serial example, " Altera Design Basics" in Chapter 3 serial examples, including source code and simulation files, etc.
uart_tr(3)
- uart_tr 异步串口通信主机 使用verilog HDL语言编写-uart_tr the host of the uart