verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in

Demo Speed通信协议MATLAB实现。基于动态帧时隙ALOHA(DFSA)协议与正交可变扩频因子码(OVSF)作为扩频码的码分多址技术相结合的超高频RFID系统-Demo Speed ​ ​ Communication Protocol MATLAB. (DFSA) agreement with orthogonal variable spreading factor code (OVSF) UHF RFID system based on dynamic frame

基于卷积编码的相频调制解调的高斯白噪声信道特性分析-Based on convolutional coding and phase frequency modulation demodulation analysis of the white gaussian noise channel characteristic

兰姆波相速度频散曲线的绘制（横轴为频厚积，纵轴为相速度），各模态的频散数据均可以导出。(Lamb wave phase velocity dispersion curve(The transverse axis is frequency-thickness products, and the vertical axis is phase velocity),and the dispersion data of each mode can be derived.)

由MATLAB计算幅频特征曲线、相频特征曲线(Calculation of amplitude frequency characteristic curve and phase frequency characteristic curve by MATLAB)