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communication_example
- 2ASK(OOK)信号的解调.svu 2ASK与MASK的功率谱.svu 2DPSK的差分编码与解码.svu 2FSK非相干解调.svu 2FSK相干解调.svu 2PSK与2DPSK调制.svu ASK的OOK法生成.svu Costas锁相环解调2DPSK.svu-2ASK (OOK) signal demodulation. Svu 2ASK MASK with the power spectrum. Svu 2 DPSK Differential encodi
数字锁相环
- DPLL
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
simple_pll_3
- simulink自制锁相环。。。。。包括一些简洁结构-PLL simulink made. . . . .
2
- 基于DSP的数字化UPS锁相设计 一篇论文-DSP-based Digital UPS lock design
pll-used-for-speed-control
- 锁相环用于电机转速精准检测，资料很不错，值得下载-Phase-locked loop for accurate detection of motor speed
costasloop
- 科斯塔斯锁相环的代码,用matlab编写,原理清楚,对于初学者很有帮助-Costas loop code, prepared by matlab, the principle clearly helpful for beginners
LPC213x_drive
- LPC213x系列底层硬件驱动函数库，包含：GPIO、UART、I2C、SPI、SSP、PWM、定时计数器、ADC、DA、实时时钟、看门狗、中断控制器、锁相环PLL、IAP等，有使用说明和源码分析。-LPC213x series of underlying hardware driver library, including: GPIO, UART, I2C, SPI, SSP, PWM, timer counter, ADC, DA, real-time clock, watchdog, in
PLL
- 用Verilog HDL编写的锁相环程序-Phase-locked loop program written in Verilog HDL