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vhdl
- 半加器 或门 1位二进制全加器顶层设计描述-Half adder or a binary gate full adder top-level design descr iption
add
- 四位无符号加法器 可以实现两个四位二进制数相加-4 unsigned adder can achieve binary sum of two 4
adder
- 这是一个四位二进制加法器,输入为两个4位二进制数,输出为5位二进制数,最高位是进位-This is a four bit binary adder, input two binary numbers 4, 5 binary output, the most significant bit is the carry-