MICRON DDR2 SDRAM芯片Verilog仿真模型以及器件编号说明

ddr3模型以及代码和测试程序，不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws

SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a re