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any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
shizhong
- 简单的VB时钟控件操作，对于刚学习VB.net的人很有帮助-VB simple clock control operation, for people just learning VB.net helpful
clock
- 电子时钟简单设计模板，内含源代码，并可实现简单计时-Electronic Clock simple design template, containing the source code, and with a simple timing
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
clockVHDL
- 电子时钟VHDL程序与仿真,详细介绍了设计的整个阶段，验证过，可以运行的。-Electronic clock and simulation of VHDL procedures, detailed design of the stage, verified, you can run.