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sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一,尽管在目前大部分设计中,广泛使用芯片厂家集成的锁相环资源,如altera 的PLL,xilinx的DLL.来进行时钟的分频,倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
ise-10
- vhdl xilinx ISE 10 Tutorial
xilinx-ISE-10.1-Quick-Start-Tutorial
- vhdl xilinx ISE 10.1 Quick Start Tutorial
xilinx-ISE-WebPACK-vhdl-Tutorial
- xilinx ISE WebPACK vhdl Tutorial
TechAss-2006
- un controller pi par le langage vhdl xilinx ise design 13.2
BH_Shi_jizhi_Out
- FPGA开发 vhdl语言 常用进制转换 基于xilinx开发平台 ISE软件-vhdl language commonly used FPGA development hexadecimal conversion based on xilinx ISE software development platform
DSSS
- 用vhdl实现基于xilinx的FPGA上的直接序列扩频通信,并且附带了matlab仿真程序。-vhdl implementation based on direct sequence spread spectrum communication on xilinx' s FPGA, and comes with matlab simulation program.