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fifo
- fifo example vhdl code
AsynchronousFIFO
- this is a source code design fifo assynchronus
123
- 该文件是16*16位先入先出fifo的源代码-The document is 16* 16-bit FIFO fifo source code
FIFO
- 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
FIFO
- FPGA内部FIFO存储器设计的vHdl源代码-FPGA internal FIFO memory design vHdl source code
fifo
- fifo的实现，通信集成电路设计的作业，包含模块源程序，源代码，适合初学者。-The realization of FIFO, communication circuit operation,Module design, test vector，source code,Suitable for beginners,Convenient experiment,Very good, right
DBfifo
- 同步FIFO设计源代码，带有复位信号的同步FIFO设计，能够在同一个时钟域范围内写入读出数据，从而做到传递数据的功效。-Synchronous FIFO design source code, synchronous FIFO design with a reset signal, can write and read data in the same clock domain range, so do efficacy data transfer.
sync_FIFO
- asynchronous fifo verilog code