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fifo
- 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能，简单易懂，并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fifo
- 一个先进先出的内存，使用一个同步时钟产生各种不同尺寸的高速缓冲-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
FIFO
- FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道，以及指示堆栈状态（满、将满等）的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be fu
fifo_syn
- 同步fifo并有详细的文档说明，希望对大家有帮助-Synchronous fifo and detailed documentation, we want to help