这是一个最简单的四位的全加器设计，由两个半加器构成，采用的是VERILOG的算法级和门级描述的。-This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descr iptions.

本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha