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VerilogHDL_forBegineer
- Verilog 语言综合实践入门, 适合初学者 很好的-Verilog language portal integrated practice, good for beginners
Verilog-Semantics
- Synthesizable Verilo---syntax and semantics一本很好的关于verilog可综合设计的参考书-Synthesizable Verilo --- syntax and semantics a good Verilog synthesis of the reference design
Synopsys SCL 10.9.3
- 后端综合软件design compiler将verilog源码,RTL文件转变成电路并实施优化