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23824648pinlvji
- 1. 测量信号:方波 ； 2. 测量频率范围: 1Hz~9999Hz 3. 显示方式: 4位十进制数显示 4. 时基电路由 555 定时器及分频器组成, 555 振荡器产生脉冲信号,经分频器分频产生的时基信号,其脉冲宽度分别为: 1s, 0.1s 5. 当被测信号的频率超出测量范围时,报警. -Measuring signal: square wave measurement frequency range: 1Hz ~ 9999Hz display: four d
Tx
- 主要是8201对音频的一些处理，包括分频和传送-8201 pairs of audio processing, including divider and transmission
75368_[www.ic5.cn]
- 74AC163可编程计数器用作分频精度高速度快-The 74AC163 programmable counters used for frequency accuracy of high-speed fast
fenpinqisheji
- 实现分频功能，用VHDL语言实现，也可适当改变参数，实现任意分频-Implementation divider using VHDL, it may be appropriate to change the parameters to achieve any divide
SWQJQ922
- VHDL语言 初始入门级教程分频器例程，50M分频为1S-The VHDL language initial entry-level tutorial
key
- 使用DCM模块对输入时钟进行分频 扫描键盘获取键值 数码管点亮 蜂鸣器驱动-使用DCM模块对输入时钟进行分频 扫描键盘获取键值 数码管点亮 蜂鸣器驱动
led
- LED 点阵点亮 对输入时钟进行分频，依次点亮相应的LED 灯-LED 点阵点亮 对输入时钟进行分频，依次点亮相应的LED 灯
Generate-X-Y-signal
- 实现输入信号的移相，分频。并可在示波器上观察李萨育图。-To achieve a phase shift of the input signal, the frequency division. And outlook on the oscilloscope Lissajous sterile Figure.
Signal-1MHz-1pps
- 实现分频处理的一个模块。从输出的1MHz信号转化为1pps信号。-Achieve sub-frequency processing module. From the 1MHz signal output into 1pps signal.
tetris
- 俄罗斯方块游戏。可改变游戏速度，实现了最简单的功能，包含分频、按键防抖，可在8*8点阵上显示。-Tetris game. You can change the speed of the game, the most simple functions contains divider button image stabilization, 8* 8 dot matrix display.
2
- 关于FPGA的分频代码,是vhdl语言编写的，可能比较简单，但比较实用。-Divider code on the FPGA
123
- 利用互信息，进行基于互信息的图像超分频重建-A Mutual Information Based Sub-Pixel Registration Method for Image Super Resolution
EDA
- 基于 CPLD/FPGA用原理图和VHDL语言混合设计实现了一多功能通用分频器。-CPLD/FPGA-based mixed schematic and VHDL language design and implementation of a multi-function universal divider.
Verilog_DIV_P
- Verilog_实现任意占空比、任意分频的方法，很有用的时序关系-Verilog_ achieve any duty, arbitrary frequency method, useful for timing relationships
PLL_100M
- 实现pll分频功能倍频功能可得到fpga说需要的频率实现多的时钟输入-Multiplier pll divide function to achieve functionality available fpga said I need to achieve multi-frequency clock input
AD
- ad转换描述unsigned char i ADMUX = 0x67 /*基准AVCC、左对齐、通道7*/ ADCSRA = 0xC2 /*使能、开启、4分频*/ while(!(ADCSRA & (1 << ADIF))) /*等待*/ i = ADCH ADCSRA &= ~(1 << ADIF) /*清标志*/ ADCSRA &= ~(1 << ADEN) /*关闭转换*/ -unsig
fenpin_clk
- FPGA的分频设计，使用spartan 3e开发板50Mhz频率，包含LED灯环节-Divide the FPGA design, use spartan 3e development board 50Mhz frequency, including LED lights links
fenpin
- 使用VHDL实现任意整数分频，包括原理以及Matlab程序。-Use VHDL to achieve arbitrary integer frequency, including schematics and Matlab program
div_clk17
- 手写时中分频，17分频，用状态机写成，之欧诺个两个过程语句简单明了易懂-Handwritten carve frequency divider 17, the state machine languages, the two processes Uno a statement, jianji8e clear and understandable
001
- 分频器的四连体数码管显示源代码以及对其分析-The four-piece divider digital display source code and its analysis