ALTERA DDR2高性能控制器使用文档，包括存储控制器、用户接口、用户测试模块，各控制信号的说明。-ALTERA DDR2 high performance controller using a document, including the memory controller, user interface, user testing module, the control signal descr iption.

This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP c

FPGA design software that easily integrates into your design flow saves time and improves productivity. The Altera® Quartus® II software provides you with a command-line executable for each step of the FPGA design flow to make the design

altera external memory interface