搜索资源列表
eIRA-LDPC-Codes-on-FPGA
- ＬＤＰＣ码的ＦＰＧＡ实现论文，外文ＩＥＥＥ文章，很有用的文献-FPGA implementation of LDPC codes Papers, Foreign IEEE article useful literature
CMMB_LDPC
- 一篇关于CMMB中LDPC编码译码的论文，解释得很详细，还有硬件(FPGA)实现方法-CMMB in an article on decoding LDPC coded paper to explain it in detail, as well as the hardware (FPGA) Implementation Method
LDPC
- 日本人关于量子密钥发送方法专利，没有被批准，此类专利国内还没有出现-Japanese patent on the method of quantum key transmission, has not been approved, such patents country has not yet appeared
Design-of-LDPC-codes-on-FPGA
- 小论文《基于FPGA的（3,6）LDPC码并行译码器设计与实现》实现了码率为1/2，帧长为1008bits的规则（3,6）LDPC码译码器-Design and Implementation of Parallel Architectures Decoder for（3,6）LDPC Codes Based on FPGA code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(S
wimax_LDPc
- 基于C++和FPGA的wimax LDPC 编译码器的设计，编码方法不同，但性能都很良好-Wimax LDPC codec based on C++ and FPGA design
ug-Model-report(2)
- LDPC model implementation on FPGA
ldpc
- 低密度校验码 ，很好用的代码，功能已经实现编码和译码-fpga ldpc
QC_LDPC_FPGA
- LDPC QC-LDPC 基于FPGA的QC-LDPC实现 论文-LDPC QC-LDPC FPGA-based QC-LDPC detailed implementation steps Thesis
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
论文
- 本资料包含目前国际顶会上关于5G LDPC译码器的FPGA实现的会议文章(This document contains an international paper on the implementation of the latest FPGA-based LDPC decoder)