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自动售货机VHDL程序与仿真
- library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_auto1 is port ( clk:in std_logic; --系统时钟 set,get,sel,finish: in std_logic; --设定、买
The-adaptive-hough-transform.r
- The adaptive hough transform（21HT） 作者：J.Kittler,自适应霍夫变换方法的作者，IEEE的原文，从图书馆找的。,The adaptive hough transform (21HT) Author: J. Kittler, Adaptive Hough Transform, author of Ways, IEEE original text, from the library looking for.
FIFO_design_reference_document
- FIFO设计的参考文档 Project name : Fifo -- Project descr iption : Fifo controller Unit 工程名 : FIFO.VHD 用到库文件IEEE.STD_LOGIC_1164-FIFO reference design document Project name : Fifo -- Project descr iption : Fifo controller Unit -
sy3
- 多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all
sy2
- 晶振频率为4.096MHz，系统同步时钟为256KHz，每个时隙占8位； 四路支路信码各为8位，分别为： 1 1 1 0 0 1 0 1 ；1 1 0 1 1 0 0 1 ；1 0 0 1 1 1 0 1 ； 1 1 1 0 1 0 1 1 ； 复接方式采用：按位同步复接。 -library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all
Library-ieee
- 本环节是建立一个数据库，使之能在扫描的同时读取所需要的信息，从而完成汉字的显示。本次设计“王、日、田、口”汉字样式设计程序如下：-This link is to establish a database that could in scanning both read required information, and thus finish the characters show. This design "king, Japan, tian, mouth" Chinese style des
chuzuche
- 一款基于VHDL的EDA计程车计费系统的设计.熟悉Quartus2操作环境-LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY liuxuanyi IS PORT(C:IN STD_LOGIC_VECTOR(2 DOWNTO 0) DP: OUT STD_LOGIC A1,A2,A3,B1,B2,B3:IN STD_LOGI
PID
- PID控制器参考，library IEEE use IEEE.STD_LOGIC_1164.ALL use IEEE.STD_LOGIC_ARITH.ALL use IEEE.STD_LOGIC_UNSIGNED.ALL -PID controller reference, libraryIEEE useIEEE.STD_LOGIC_1164.ALL useIEEE.STD_LOGIC_ARITH.A
vhdl
- library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2
library-IEEE
- pid controller design for implementation in xilinx for controlling dc motor speed using feedback which is obtained through optical sensor -pid controller design for implementation in xilinx for controlling dc motor speed using feedback which is obta
LIBRARY-ieee
- A WORD FILE ON FULL ADDER
vhdlll
- 八位数码管扫描显示程序，要求显示12345678 间隔四秒显示56789ABC 间隔四秒显示3456789A 再隔4秒显示 -LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY chenyongqiang IS PORT ( CLK : IN STD_LOGIC SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) 段控制信号输出