搜索资源列表
Adaptive-digital-filter
- 自适应数字滤波器中乘法器的硬件设计，用VHDL语言实现自适应数字滤波器。-Adaptive digital filter in multiplier hardware design, using VHDL language adaptive digital filter.
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
mult2
- this the multiplier 2 module for the reed solomon encoder-this is the multiplier 2 module for the reed solomon encoder
mult4
- this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder
DDS-baseddesignofthesinusoidalsignalgenerator
- 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the singl
FPGA
- 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processin
yibuqingling
- VHDL verilog 乘法器异步清零-VHDL verilog multiplier Asynchronous Clear
multifreqvhdl
- 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。-According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe tha
ECC
- 一种并行的有限域乘法器结构，用于ECC系统构建，多项式基-A parallel Finite Field Multiplier Architecture for ECC system construction, polynomial basis
32X32MULTIPLIER
- implementation of 32x32 multiplier using vhdl language
multiply
- 本文利用全加器、半加器，利用进位保留的思想，在前向割集中加入四级流水实现了乘法器的设计，提高乘法器的运算速度，并且介绍了乘法器的VHDL的程序编写过程以及代码，并给出了仿真波形-In this paper, the use of the full adder, half adder using carry-save ideological forward cutset added four water to achieve a multiplier design, to improve the
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
Test_multiplier
- this is fast complex multiplier in vhdl
Booth Multiplier
- I have uploaded the introduction of the booth multiplier project in VHDL code. IF anyone interested on this code give me a shout and i will upload the whole code in here.
Wallace_tree_Final
- 16bit wallace tree multiplier..VHDL source
multiliplier
- Braun multiplier VHDL code
simfahm
- booth multiplier full code the code is tested and runs on vhdl -booth multiplier full code the code is tested and runs on vhdl booth multiplier full code the code is tested and runs on vhdl
Booth
- This file contains all the entity-architectures for a complete k-bit x k-bit Booth multiplier. the design makes use of the new shift operators available in the VHDL-93 std -This file contains all the entity-architectures for a complete k-bit x k-bit