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v4_ddr_sdram_controller
- 利用v4fpga实现sdram ddr控制器设计，很详细的，很实用的资料
cyclone_ug_ddr_sdram
- ddr——sdram
mx27ads_x33
- i.mx27开发板的整套详细原理图，包括：DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST,FEC PHY, UART,JTAG等等接口-i.MX27 development board schematic details of the package, including: DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST, FEC PHY, UART, JTAG interface,
DDR
- 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
K4H511638脰D
- Data Sheet 512Mb D-die DDR SDRAM Specification
SDRAM_and_DDRrouting
- SDRAM与DDR布线指南 SDRAM与DDR布线指南
DDRSDRAMcontroller
- DDRⅡ+SDRAM控制器设计实现相关学问论文，希望对基于ＦＰＧＡ实现ＳＤＲＡＭ控制的有所帮助-DDRⅡ+SDRAM ｃｏｎｔｒｏｌｌｅｒ.rar
K4H511638D
- 512Mb D-die DDR SDRAM Specification
TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
SDRAM
- 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
DDRdesigen.pdf
- DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
ddr_sdr_V1_1
- its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
sdram_introduce
- sdram内存技术指南（sdr,ddr,ddr2,ddr3）-sdram memory technology guide (sdr, ddr, ddr2, ddr3)
Datasheets
- Mobile DDR SDRAM MT46H32M16LF – 8 Meg x 16 x 4 banks MT46H16M32LF/LG – 4 Meg x 32 x 4 banks TFT-G240320LTSW-118W-E 16-megabit 2.5-volt or 2.7-volt DataFlash K9F1G08X0A S25FL032P S25FL032P Cover Sheet 32-Mbit CMOS 3.0 Volt Flash Memory
DDRSDRAM
- 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
JESD79-3E
- This document provides implementation instructions for the DDR3 interface-This document defines the DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this
DDR-SDRAM-design-and-debugging
- DDR SDRAM设计及调试经验总结 DDR SDRAM设计及调试经验总结-DDR SDRAM design and debugging Experience
K4X2G323PC-8GC6(D8)_R09
- K4X2G323完整数据手册，三星DDR SDRAM芯片，128MB-K4X2G323 datasheet
code
- DDR RAM DEscr iptION CODE AND DOCUMENT