通过VHDL编程，在FPGA上实现计数器1至16的计数功能-Count from 1 to 16 by VHDL on FPGA

CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des

本程序使用vhdl开发的实现四位计数器的功能。(This program uses VHDL developed to achieve the function of four counters.)