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17bit_Smart_Absolute_Encoder.z
- 多摩川17bit绝对值编码器的NRG协议文档，配合上传的解码源程序，采用半双工的通信模式。,Tamagawa 17bit absolute encoder NRG agreement documents, with the upload source decoder, using half-duplex communication mode.
2_4decoder
- 2_4 decoder that file contain vhdl code of decoder
7decoderdesigndigitaldisplay
- 1.学习7段数码显示译码器设计。 2.进一步熟悉VHDL设计技术,掌握CASE语句的使用。 3.掌握文本输入法的顶层设计方法。 -1. Learning 7 decoder design digital display. 2. More familiar with the VHDL design techniques, master the use of CASE statements. 3. Have the text input method of the top-level d
ppm
- ppm是通信类系统比较重要的前段部件，本设计只给出vhdl的代码实现，并给出测试。-ppm decoder
mpeg
- mpeg encoder and decoder
DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
8b10b_encdec
- 8b/10b encoder/decoder vhdl source-8b/10b encoder/decoder vhdl source
vit_dec
- viterbi decoder implementation
fwdrsapapers
- Fpga Based Enviuronemen paper format that includes Viterbi Decoder complete VHDL code for the document . Nh format -Fpga Based Enviuronemen paper format that includes Viterbi Decoder complete VHDL code for the document paper format that include
mp3-decoder-using-VHDL
- mp3 decoder using vhdl...it s very easy to implement using xilinx
aaa
- 用verilog vhdl 编写的 38译码器，包括源代码和测试模块-38 decoder
vhdl
- 行为描述、数据流描述、结构描述实现2to4译码器。-Behavior descr iption, descr iption of the data stream, 2to4 decoder schema.
decoder
- vhdl语言编写的7段数码管译码器，包含了全部代码和工程图-7-segment LED decoder vhdl language contains all the code and drawing
vhdl
- library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2
sanba
- 三八译码器实现和应用，通过vhdl实现一个简单的三八译码器电路-Thirty-eight decoder implementations and applications, through the realization of a simple vhdl thirty-eight decoder circuit
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
dekoder_el
- VHDL DECODER FOR FPGA
01316017
- investigating the performances and complexities of the various SISO algorithms. a turbo decoder with the selected SISO algorithm is designed and implemented using VHDL as design entry and simulation language
two_to_fourdecoder
- two_to_four decoder using vhdl