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VerilogHDL-DDR2SDRAM
- 关于DDR2 控制器的设计 是通过verilog语言设计-DDR2 controller design through verilog language design
DDR2-controller
- My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another