搜索资源列表
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
matlab
- 开题报告哦啊 我精心设计的 希望大家喜欢 任意波形发生器-Oh ah problem that the report carefully designed my hope that everyone likes Arbitrary Waveform Generator
pal.rar
- PAL制式时序发生verilog模块，13.5MHz，频率可以改,PAL video timing generator verilog modules, 13.5MHz, the frequency can be changed
Verilog_HDLsequence-generator
- Verilog序列产生器，内有代码，可产生随机序列-Verilog sequence generator, which have code that generates random sequences
VERILOG_code_for_any_wave_dds
- 编写verilog程序来完成dds，控制任意波形的生成-Write verilog program to complete dds, arbitrary waveform generator control
mysunrom
- FPJA的verilog 正弦信号发生器-sinusoidal signal generator verilog