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synopsis_FSM_coding
- synopsis的有限状态机编码方法的文档。 针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。 FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the in
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
SMCodingStyles
- verilog state machine coding style
FSMFundamentals
- Implementation of a Finite State Machine in Verilog !
floatmul
- 用verilog实现三十二位浮点数算法，通过状态机的方法实现。-32 floating-point implementation using verilog algorithm, the method adopted by the state machine implementation.
VerilogCh4
- VHDL and Verilog code referrals tools, EDA staff to be very helpful. vend machine
Advanced_Verilog_Design
- 以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, b
zhuangtai
- Verilog语言实现状态机的设计，实现的状态机总共有三种，均给出了具体的实现方案-Design and implementation of the state machine of the Verilog language, the state machine to achieve a total of three, were given a concrete implementation scheme
Verilog
- Verilog课程设计自动售货机 1）设计一个自动售货机，此机能出售1.5元、2元两种商品。出售哪种商品可有顾客按动相应的一个按键即可，并同时用数码管显示出此商品的价格。可同时购买两种、多件商品。 2）顾客投入硬币的钱数有5角、1元两种。此操作通过按动相应的两个按键来模拟，并同时用数码管将投币额显示出来。 3）顾客投币后，按一次确认键，如果投币额不足时则报警灯亮。如果投币额足够时自动送出货物（送出的货物用相应不同的指示灯显示来模拟），同时多余的钱应找回，找回的钱数用数码管
washmachine
- 基于FPGA的洗衣机控制器 verilog语言 实现注水 脱水，正反转反复控制 状态机-FPGA-based controller verilog language washer water dehydration, reversing repeated control state machine
vendingmachine_verilog
- This file is solution of project that can make vending machine in language of verilog (also can be activated in altera cyclone2 board)
Vending-machine
- Vending machine based on verilog.
verilog-ieee
- The Verilog ¤ Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it
auto_seller_verilog
- 自动售货机的verilog实现，文档中有设计自动售货机的要求，下面附有代码的实现以及仿真波形-Vending machine verilog achieve, there is a document designed vending machine requirements, implementation and simulation waveforms with the following code
part1FSM
- Verilog implementation of a Finite state machine. Part1 of lab 7 altera de2115 lab. -Verilog implementation of a Finite state machine. Part1 of lab 7 altera de2115 lab.
14_ethernet_test
- 千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
autosell
- 基于FPGA的自动售货机，有两种商品，每种都是1.5元，可以投入1元和五角两种货币。(A vending machine based on FPGA,)