搜索资源列表
On-Linear-and-Quadratic-Elements-with-mixed
- Solid-shell elements form a class of fi nite element models intermediate between thin shell and conven- tional solid elements. They have the same node and freedomconfi guration of solid elements but account for shell-like behavior in th
Automatic-adaptation-of-an-integration-formula-in
- Solid-shell elements form a class of fi nite element models intermediate between thin shell and conven- tional solid elements. They have the same node and freedomconfi guration of solid elements but account for shell-like behavior in th
AXE050-Tutorial-Board
- AXE050 Tutorial Board仿真好的图-AXE050 Tutorial Board simulation good Figure
AXE107-Rudolph
- AXE107 Rudolph 仿真成功的图-AXE107 Rudolph simulation successfully Figure
Freqout
- 关于 Freqou 的仿真成功的图 可以供参考-Figure Freqou successful simulation can be used for reference
Craftsmen-notes
- 分段线性插值法的思想精髓是， 把曲线看作若干段首尾相连的直线 段；根据每段直线的斜率来求算该线段所在区段内的数据值。相邻两 个线段的接点称为标定点。由下图可知，当标定点选择合理时，计算 结果可以非常接近实际值。 -The spirit and essence of the piece-wise linear interpolation curve as several segments of the end-to-end straight-line segment calc
51
- 基于51单片机开发板的电路程序图，51单片机是学习单片机最基础的入门。-Figure 51 MCU development board circuit program, 51 MCU is the most basic entry-learning microcontroller.
USB_HID_Report_demo
- HID的报告描述符巨难懂，关键是数据格式与每一位代表的意思。经过三天的研究，终于将HID Report的每一个数据位的含义弄清楚了，现将数据解析如下，最后附上了一个HID 通信的Report例子-HID report descr iptor huge and difficult to understand, the key is a data format every representative of the mean. After three days of research, and fi
30-PLC
- 30种PLC电缆制作图 30种PLC电缆制作图 下别人的-Under 30 PLC cable making 30 kinds of the PLC cable production Figure others
sin
- vhdl语言写的基于rom的正弦波发生器，包含代码和仿真图-VHDL language used to write rom-based sine wave generator contains code and simulation Figure
detector
- vhdl语言写的状态机，完成序列检测的功能，包含代码和仿真图-VHDL language used to write the state machine, complete sequence detection features, including code and simulation Figure
CD4.12-P374493
- The code added to Figure 4.12.1 to handle bypassing is highlighted
HCS12X_PE
- 其实HCS12X的时钟很简单，比起ARM，甚至是HCS08的8位MCU，就是一个PLL和BUS COLOCK之间的换算。 很多不人愿意看DATASHEET，图太多了，寄存器也是样不多一个样子，所以往往导致程序出问题。 但是，时钟，CRG这块很重要，是一切模块的基础。 那么，如果你不愿意write code，那么就generate code吧。 -Fact, HCS12X clock is very simple compared to ARM, even HCS08 8-bit
tu
- 实验要求：（1）理解图顶点和边的存储方法：邻接矩阵和邻接表；（2）理解图的遍历算法，掌握其应用；（3）应用图的遍历算法判断图是否连通和两顶点间是否存在路径。-Experimental requirements: (1) to understand the storage method: Figure the vertices and edges adjacency matrix and adjacency list (2) to understand graph traversal algor
jsmindmap
- js的思维导向图 js thinking oriented Figure-js thinking oriented Figure
Weighted-linear-fit.m
- Weighted linear fit: it calculates correlation coefficient and fit parameters and it makes a final figure.
Generate-X-Y-signal
- 实现输入信号的移相，分频。并可在示波器上观察李萨育图。-To achieve a phase shift of the input signal, the frequency division. And outlook on the oscilloscope Lissajous sterile Figure.
Georgiou-verilog
- The code added to Figure 4.12.1 to handle bypassing is highlighted
CHU92A
- MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
cemmpic.rar
- 用VISIO画的环保数据采集平台工作图,自认为画得还可以，发上来凑5个,Figure VISIO painting environmental data acquisition platform, since that can also be painted, made up Minato 10