本实验是VHDL的触发器实现，将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成在一个CPLD芯片中模拟其功能，并研究其相互转化的方法。-This experiment is the trigger of VHDL realize, will be basically RS flip-flop, synchronous RS flip-flop, the integrated JK flip-flop, D flip-flops simultaneously integrate

Write VHDL specifications for an eight bit twisted ring counter based on each of the designs in the previous problem. Look at the synthesis report generated by the design tools (use the Spartan 2 xc2s15-cs144-6 part for this). How many fli