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介绍用于光纤通信的速率为2.5 Gb/s的高速RS(255,239)译码器设计。对输入信号中可能出现的超
出译码器纠错能力的误码可进行检测判断,保证了误码不扩散。对译码器中大量使用的有限域乘法器进行了优化设计,尤其对并行钱氏搜索电路中的乘法器采用了按组优化设计方法,与直接实现方法相比,复杂度降低了45 -For optical fiber is introduced at a rate of 2.5 Gb/s (255239) of the high speed RS decoder des
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The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture base
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2. Novel High Speed Vedic Mathematics Multiplier
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The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
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vedic multiplication is used to implement on FPGA. here the vdic multipler uses urdhwa tiryakhbyam sutra to multiply 16 bit numbers, which is applicable for all data type numbers.
This uses vertical and cross wise multiplication process.
The out
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AN FPGA BASED HIGH SPEED IEEE-754 DOUBLE PRECISION FLOATING POINT MULTIPLIER
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