搜索资源列表
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- 關於LDPC的encoder和decoder設計的最新參考資料，將QCLDPC同MIMO系統很好的結合在一起-LDPC on the encoder and decoder design of the latest reference materials, will be the same MIMO system QCLDPC good combination
thesis04_dul98
- LDPC decoder thesis with development details
DEv_LDPC
- Development of LDPC Encoder/Decoder core
MultiMode_LDPC_Decoder_Design_for_Mobile_WiMAXSys
- MultiMode LDPC Decoder Design for Mobile WiMAXSystem
dec
- ldpc decoder design for research project
LDPCDecoderImplementation
- LDPC decoder implementation
ldpc_rec_dec
- LDPC码的编译码程序，用的是LU分解算法，和BP译码算法，在Matlab上调试通过-LDPC encoder and decoder
ldpc-matlab
- 关于ldpc的编解码的相关程序，欢迎大家下载，大家要多多共享资源啊-Ldpc codec on the relevant procedures, are welcome to download, we have to a lot of shared resources ah
fldpc
- Flexible ldpc decoder implementation
LDPC-Decoder
- This is a report on Low Density Parity check with a sample source code descr iption on an example. The theory part can be helpful to those who wish to work further in LDPC.
Design-of-LDPC-codes-on-FPGA
- 小论文《基于FPGA的（3,6）LDPC码并行译码器设计与实现》实现了码率为1/2，帧长为1008bits的规则（3,6）LDPC码译码器-Design and Implementation of Parallel Architectures Decoder for（3,6）LDPC Codes Based on FPGA code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(S
New-Decoding-Methods-for-LDPC-Codes-on-Error-and-
- This my research about Error fixing. For low-end devices with limited battery or computational power, low complexity decoders are beneficial. In this research we have searched for low complexity decoder alternatives for error and error-erasu
codefroge-ldpc-matlab
- this an implementation of ldpc encoder and decoder in matlab. generator matrix, parity check matrix and the chennel are implemented seperately. the bit error rate performance is estimated for the ldpc code -this is an implementation of ldpc encoder a
LDPC-code
- LDPC encoder and the decoder of sum-product algorithm. (input H matrix form is Mackay s website form)
put
- Efficient LDPC Decoder Implementation for DVB-S2 System
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
Decoder-Optimised--Growth-
- 一种新型的建筑不规则低密度 奇偶检验基于所述修改（LDPC）码 渐进边增长（PEG）的算法。边缘 所述PEG算法的位置是由利用所述Sum-增强 积算法在奇偶校验矩阵的设计。该 提出的算法是在块长度和速度非常灵活。 被提议的方法构建代码的测试 AWGN信道和显著的性能改进 实现。建议解码器优化的灵活性 动作，然后由它的使用在修改所述改进的示 PEGIPEGI）算法来实现进一步的性能提升。-A novel construction for irregular
LDPC
- 实现LDPC编码仿真和译码仿真，参数有接收码字，解调器输出，信道噪声标准差，校验矩阵，迭代次数-realise the encoder and decoder of LDPC,ceremeters include receiveword,sigma,check parity,IterNum
06018325
- A Nonbinary LDPC Decoder Architecture With Adaptive Message Control
论文
- 本资料包含目前国际顶会上关于5G LDPC译码器的FPGA实现的会议文章(This document contains an international paper on the implementation of the latest FPGA-based LDPC decoder)