搜索资源列表
TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
fft2
- a 4 point fft is designed using a pipelined architecture
FPGA-DESIGN-OF-A-HARDWARE-EFFICIENT-PIPELINED-FFT
- The digital wideband receiver is a critical component in modern digital receivers. The receiver has the capability to expose and distinguish adverse signals contained within a large bandwidth (on the order of 1 GHz or more) of the radio frequency (RF
06118316
- Pipelined Radix- Feedforward FFT Architectures
gh
- IMPLEMENTATION OF FAST SDC-SDF PIPELINED FFT USING CSD MULTIPLIER