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自动售货机VHDL程序与仿真
- library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_auto1 is port ( clk:in std_logic; --系统时钟 set,get,sel,finish: in std_logic; --设定、买
Dual_port_RAM
- 很精彩的双端口RAM应用笔记，对搞单片机、FPGA的都有帮助。-dual_port_ram
20060510191318991
- ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
TopLevel_DualPort_Ram_XilinxCore
- Top Level Dual Port Ram Core Project, VHDL code
USB2RAM
- Module usb ram - bardzo uzyteczny do komunikacji z innymi urzadzeniami-Module usb ram- bardzo uzyteczny do komunikacji z innymi urzadzeniami
RAM
- 使用ISE的XST综合，综合结果使用了Block RAM，当然有时对于用到的容量很小的RAM，我们并不需要其使用Block RAM，那么只要稍微修改一下就可以综合成Distribute RAM-The use of ISE s XST synthesis, the combined result of the use of the Block RAM, it is our expectation. Of course, sometimes the capacity to use a very s
spartan6_fpga_blockram_user_guide
- Spartan6 FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
single-clk-syncram-asyncrd
- Aplication with RAM sincronous in VHDL
RAMinVHDL
- How to create a RAM memory in VHDL