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电子九阴真经
- 《DSP芯片的原理与开发应用》 《通过在FPGA设计流程引入功率分析》改善PCB的可靠性 《如何快速解决PCB设计EMI问题》菜鸟入门必看 《CADENCE射频SiP方法学套件加速无线应用设计》 《如何有效地管理FPGA设计中的时序问题》 《利用微型热管理和电源管理技术》解决电子设计的关键难题 最新射频IC应用编程接口设计方案 《DC/DC电源管理应用中的功率MOSFET的热分析方法》有效的解决方法 《基于PSoC3芯片的步进电机微步控制方案》经典案例 《SVN，HG，GIT命
Equalization_in_high-speed_communication_systems.r
- 高速通信系统中均衡器的几种结构说明与比较，对设计SerDes的朋友有帮助-High-speed communications systems equalizer descr iption and comparison of several structures, the design SerDes friends help
How_to_apply_serdes
- 关于SerDes应用的研究，切合当前发展的现状，给出来很好说明-SerDes applications on the research, meet the current development status, to come out very good descr iption
StratixGX
- Stratix GX器件在SDH宽带交换中的应用-Stratix SDH serdes
Multi_Gigabit_transceiver
- A Multi-Gigabit Transceiver (MGT) is a SerDes capable of operating at serial bit rates above 1 Gigabit/second. MGTs are used increasingly for data communications because they can run over longer distances, use fewer wires, and thus have lower costs t
designcon2004_serdes
- DESIGN CON SERDES PDF DOCUMENT
serdes_handbook
- 一篇serdes文章手册，简单列举了一些Serdes应用和测试，具有一定的参考意义-a file about serdes
6.25g_dfe
- 高速数字传输技术, 时钟提取，均衡，高速采样 -high speed serdes， clock and data recovery, equalization, high-speed sampling
sorna_agc_serdes
- 高速数字传输技术, 时钟提取，决策反馈均衡，高速采样, -high speed serdes， clock and data recovery, decision feedback-equalization, high-speed sampling
jesd204b
- 高速Serdes接口协议规范，包括电器层，传输层，数据链路层。传输层包括组帧方式，加扰，字节替换等内容，数据链路层包括Tx和Rx设备的握手通信协议-Speed Serdes interface protocol specifications, including electrical layer, transport layer, data link layer. Transport layer including group frame mode, scrambli
xapp882
- This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionall
SoftSerDes_FPGA
- 软件实现serdes的FPGA设计方法，非常有价值-FPGA design software serdes of
decoder-SerDes
- 介绍了8b/10b SerDes 中数字模块的设计和验证，这些数字模块 包括：8b/10b 编解码器、Comma 检测器和串并/并串转换电路。-This article introduces theories and applications of four types of SerDes architecture, and establishes the design of 8b/10b SerDes interface circuit through a top-down des
SerDes
- 12．5 Gb／s半速率时钟数据恢复电路(CDR)的 设计及6．25Gb／s SerDes接收芯片的系统集成，设计工艺均为TSMC 0．189in CMOS工艺。-aspects：Design of Half-rate 1 2．5 Gb／s Clock Data Recovery (CDR)and Integration of 6．25Gb／s SerDes receiver．Both are realized in TSMC 0．1 89m CMOS process．
four-channals-3.125G-SERDES
- 介绍SERDES接口中频率合成器和时钟恢复电路的设计-The first key issue is frequency synthesizer and clock recovery circuit design．
JIEKOU
- 为你详细介绍各种接口的芯片选型，接口类型如1394 CAN Crosspoint Display ESD/EMI I² C Isolation LVDS/M-LVDS Optoelectronics PCIe RS232/422/485 SerDes UARTs USB Voltage-Level Translation xECL，为你解决常用接口的设计难题，提供各种接口的原理图设计-You detail the various interface chip selection, int
SERDES-TransmitterReceiver-(ALTLVDS)-Megafunction
- 1. It creates an 8-bit general purpose ( GP ) output port, controlled by any character received on the serial port.