搜索资源列表
Static_Timing_Analysis
- Altera Quartusii静态时序分析（Static Timing Analysis）基础及应用
DDR
- 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
Max_plus
- Max_plus_的时序仿真与时序分析,教程。详细讲解了实习仿真方法-Max_plus_ timing simulation and timing analysis, tutorials. Detailed account of practical simulation method
Static_Timing_Analysis
- 静态时序分析设计的经典教程书籍 全面，权威的讲解，丰富的内容举例-Static timing analysis tutorial books classic design a comprehensive, authoritative presentation, rich content, for example
LTE_transmition_technoiques
- 分析了LTE系统频率偏移，定时误差，信道估计问题等，并对广义Rake接收机和CPEDS接收机的性能做了比较。-Analysis of the LTE system frequency offset, timing error, channel estimation problems, and generalized Rake receiver performance receiver and CPEDS were compared.
CadenceTimingAnalysis
- 使用Cadence进行PCB时序分析好文章，对于学习SI仿真有很大的用处。文章很实用。-Cadence timing analysis a good article, for the rest SI simulation is very useful. Very useful article
FPGA-Timing-Function-Model-Analysis_1
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(I).
FPGA-Timing-Function-Model-Analysis_3
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(III).
PrimeTime_Advanced_Timing_Analysis_User_Guide
- PrimeTime Advanced Timing Analysis User Guide
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
pi-proj-final-doc
- reedsolomonencoder design simulation and timing analysis using synopsys tools
pt_fundamentals_ug
- 文献包含PT的时序分析方法说明： PrimeTime is a full-chip, gate-level static timing analysis tool targeted for complex, multimillion-gate designs. It offers an unsurpassed combination of speed, capacity, ease of use, and compatibility with industry-standard da
verilog-uart
- UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
sdram_ov7670_vga
- OV7670的资料，包括时序分析，和注意事项，能够很好地进行开发-OV7670 information, including timing analysis, and precautions that can be good for development
LCD1111
- LCD时序分析解疑.zip主要是针对嵌入式常用的TFT-LCD进行时序分析-LCD Timing Analysis eliminating. Zip mainly for timing analysis for embedded common TFT-LCD
sdram_interface_tm
- SDRAM接口时序和pcb布线长度分析， -SDRAM Interface Timing Analysis and pcb wiring length
timing
- FPGA设计时序约束及时序分析资料。详细介绍了时序约束中的基本概念、常用约束、如何分析时序等。-FPGA design timing constraints and timing analysis. Details of the timing constraints of the basic concepts, common constraints, such as how to analyze timing.
physicalDesign
- IL2200ASIC Design Physical Implementation Styles ASIC Design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification and Ener
altera-timing
- Altera时序分析基础，帮助提升时序分析能力，建立时序分析模型。-The base of Altera timing analysis.
Static Timing Analysis
- 静态时序分析，有很详细的例子和图标说明，对于FPGA工程师非常有用，对于IC工程师也非常有用！(Static timing analysis, there are very detailed examples and icon descr iptions.)