搜索资源列表
risc8
- 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
DDR_SDRAM_controller_verilog
- DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），
verilog数字时钟论文及代码
- verilog数字时钟论文及源代码
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
chengfa
- 实现乘法功能，用verilog语言可以编译的乘法程序源代码-The realization of multiplication functions, verilog language can be used to compile the source code of the multiplication process
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
verilog
- verilog的各种编程实例 有源代码的从简单到复杂-verilog source code of various programming examples from the simple to the complex
chuanbing
- 串并转换器的verilog源代码带testbench文件-String and converter verilog testbench file with the source code
mux_case
- 用case 语句描述的4 选1 MUX源代码程序实现-case4（1） ，VHDL&verilog
traffic
- 绿灯、黄灯和红灯交通指示灯的verilog HDL程序源代码-traffic lamp ，red,yellow,green,verilog HDL
clock
- 多功能数字钟的Verilog ＨＤＬ源代码程序的实现-ｍｕｔｉｌ－ｆｕｎｃｔｉｏｎ ｄｉｇｉｔａｌ ｃｌｏｃｋ Verilog ＨＤＬ
aaa
- 用verilog vhdl 编写的 38译码器，包括源代码和测试模块-38 decoder
FPGA-Prototyping-By-Verilog-Examples
- 本书介绍了大量的经典的FPGA开发实例，并附有源代码，是一本很难得外文书籍。-This book presents a classic instance of the FPGA development, together with the source code, it is difficult to get a foreign language books.
rmii
- rmii 以太网接口时序源代码，值得开发借鉴的哦-verilog hdl
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
DDS-Verilog
- DDS设计的源代码 用于生成高精度的DDS程序 VERILOG-VERILOG DDS DDS program design source code used to generate high-precision
frequency-agility
- 本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果-The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation
Cy7C68013_SLAVE-FIFO_Verilog
- 针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code
costas-loop-in-ISE
- ISE软件中实现costas环的方案，使用语言为verilog。文件为word形式，不含有源代码，只包含实现过程及注意事项。-ISE COSTAS LOOP