搜索资源列表
chengfa
- 实现乘法功能，用verilog语言可以编译的乘法程序源代码-The realization of multiplication functions, verilog language can be used to compile the source code of the multiplication process
verilog-code-for-8bit-multiplier-using-vedic-algo
- The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.