搜索资源列表
FPGAFIR
- FPGA-based high-order FIR filter design
103244864FIR_filter_DA_machine
- 简易fir滤波器，采用分布式算法实现，verilog-Simple fir filter using distributed algorithm, verilog
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
FIR
- FIR filter using verilog code
8-channel-FIR
- b channel FIR filter verilog
verilog
- 最长的那个句子，求sum的赋值语句就是FIR滤波器的计算过程，将二进制乘法转化为移位运算。对于小数点后的乘数是向左移，小数点前的乘数是往右移位。 -The longest sentence, find the sum of the assignment statement is the calculation of the FIR filter, the binary multiplication into shift operation. Multiplier after the deci
filter
- verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
high-pass-filter-design
- 基于verilog的高通fir数字滤波器设计-Verilog fir digital high-pass filter design based on
CODE-for-FIR-filter
- code for FIR filter using verilog hardware descrption language